The present invention is directed to integrated circuits and their processing for the manufacture of semiconductor devices. More particularly, the invention provides a method and device for a non-volatile memory (NVM) device having nanocrystalline silicon hillock floating gates and high K tunneling dielectric. Merely by way of example, the invention has been applied to provide high programming efficiency and data retention characteristic for a non-volatile memory device. But it would be recognized that the invention has a much broader range of applicability. For example, the invention can be applied to integrated circuits incorporating embedded non-volatile memories or memory card applications.
As semiconductor device feature size continues to scale down to nanometer regime, conventional floating gate non-volatile memory (NVM) devices have difficulty in maintaining device performance. To fabricate devices beyond current scaling limits, integrated circuit manufacturers are rigorously exploring alternative materials and device structures.
Integrated circuits or “ICs” have evolved from a handful of interconnected devices fabricated on a single chip of silicon to millions of devices. Current ICs provide performance and complexity far beyond what was originally imagined. In order to achieve improvements in complexity and circuit density (i.e., the number of devices capable of being packed onto a given chip area), the size of the smallest device feature, also known as the device “geometry”, has become smaller with each generation of ICs. Semiconductor devices are now being fabricated with features less than a quarter of a micron across.
Increasing circuit density has not only improved the complexity and performance of ICs but has also provided lower cost parts to the consumer. An IC fabrication facility can cost hundreds of millions, or even billions, of dollars. Each fabrication facility will have a certain throughput of wafers, and each wafer will have a certain number of ICs on it. Therefore, by making the individual devices of an IC smaller, more devices may be fabricated on each wafer, thus increasing the output of the fabrication facility. Making devices smaller is very challenging, as each process used in IC fabrication has a limit. That is to say, a given process typically only works down to a certain feature size, and then either the process or the device layout needs to be changed. An example of such a limit is non-volatile memory devices for the manufacture of integrated circuits in a cost effective and efficient way.
Fabrication of custom integrated circuits using chip foundry services has evolved over the years. Fabless chip companies often design the custom integrated circuits. Such custom integrated circuits require a set of custom masks commonly called “reticles” to be manufactured. A chip foundry company called Semiconductor International Manufacturing Company (SMIC) of Shanghai, China, is an example of a chip company that performs foundry services. Although fabless chip companies and foundry services have increased through the years, many limitations still exist. For example, as logic devices are scaled and designed to operate under lower voltages, non-volatile memory devices are difficult to scale down and continue to need high voltages to operate.
Non-volatile MOSFET memory devices based on nano-crystalline (NC) silicon floating gates have been reported as an alternative to conventional floating gate NVM devices. Nanocrystalline floating gates can provide good device performance, such as low power consumption, high writing endurance, good programming and erase performance and small device size. Such device has become a candidate for next generation NVM memory.
However certain limitations still exist with nano-crystalline floating gate devices. Because nano-crystalline floating gates are less sensitive to defects in the tunnel oxide, thinner tunnel oxides can be used in a non-volatile memory device. Low voltage and high programming efficiency can therefore be achieved. However, a thin tunnel oxide is prone to charge leakage and degraded data retention. Therefore convention non-volatile memory devices with SiO2 tunneling barrier are limited by the trade-off between programming efficiency and data retention. In addition, it is difficult to grow nano-crystalline (NC) silicon material and to control the size and shape of the NC dots (particles). This leads to difficulties in control of the program and erase characteristics of the device.
From the above, it is seen that an improved technique for processing semiconductor devices is desired.